The following figure shows the Shared Logic tab.
Figure 1. Shared Logic
- GT Wizard Option
- You can select include GT Wizard in the example design and then the GT Wizard IP will be delivered into the example design area. You can reconfigure the IP for further testing purposes. By default, the GT Wizard IP will be delivered in the PCIe IP core as a hierarchical IP and you cannot re-customize it. For signal descriptions and for other details, see the UltraScale Architecture GTY Transceivers User Guide (UG578) or UltraScale Architecture GTH Transceivers User Guide (UG576).
- GT COMMON Option
- This option is used to share the GT COMMON block used in the design when
Gen2 (PLL Selection is QPLL1) and Gen3
link speeds are selected.
- When Include GT COMMON in example design is selected, GT common block instance will be available in the support wrapper, which is inside the AMD top file and can be used either by the core or the external logic.
- When Include GT COMMON inside GT Wizard is used, GT COMMON can be shared by external logic.
- When No Sharing when inside GT Wizard and PCIe is selected, no sharing of GT COMMON block is allowed.
- When Include GT COMMON in example design and Include GT Wizard in example design are selected together, you must use the latest GT COMMON settings from the example design project of the GT Wizard IP of the same configuration. This specific option delivers static GT COMMON wrappers which have the latest settings for the 2017.3 time frame only.