In order to simulate the PCIe IP when Tandem Configuration is enabled, specific parameters must be set to define the behavior of the core. Users must set properties to disable the MCAP stage1/stage2 design switch. This will allow simulation to run as though stage 2 is loaded, but will not simulate design switch behavior from the MCAP registers. If forcing internal signals is not desired, the +define+SIMULATION directive can also be set in the compiler as an additional option instead.
The properties to disable are these:
defparam board.EP.pcie4_uscale_plus_0_i.inst.MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE";
defparam board.EP.pcie4_uscale_plus_0_i.inst.MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE";
defparam board.EP.pcie4_uscale_plus_0_i.inst.MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE";
defparam board.EP.pcie4_uscale_plus_0_i.inst.MCAP_ENABLEMENT = "NONE";These properties are found in the example design testbench file. To access:
- Open the IP example design from the generated core.
- Locate and open the top-level testbench file, board.v.
The instance names will match the generated core.