Simulation Design Overview - 1.3 English

UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213)

Document ID
PG213
Release Date
2023-10-19
Version
1.3 English

For the simulation design, transactions are sent from the Root Port Model to the core (configured as an Endpoint) and processed by the PIO example design. The following figure illustrates the simulation design provided with the core. For more information about the Root Port Model, see Root Port Model Test Bench for Endpoint.

Figure 1. Simulation Example Design Block Diagram