The core and example design contain ports (signals) specific to Tandem Configuration. These signals provide handshaking between stage 1 (the core) and stage 2 (the user logic). Handshaking is necessary for interaction between the core and the user logic. The following table defines the handshaking ports on the core.
| Name | Direction | Polarity | Description |
|---|---|---|---|
| mcap_design_switch | Output | Active-High |
Identifies when the switch to stage 2 user logic is complete. 0: Stage 2 is not yet loaded. 1: Stage 2 is loaded. |
| cap_req | Output | Active-High | Configuration Access Port arbitration request signal. This signal should be used to arbitrate the use of the FPGA configuration logic between multiple user implemented configuration interfaces. If the Media Configuration Access Port (MCAP) is the only user implemented configuration interface used, this signal should remain unconnected. |
| cap_rel | Input | Active-High | Configuration Access Port arbitration request for release signal. This signal should be used to arbitrate the use of the FPGA configuration logic between multiple user implemented configuration interfaces. If the MCAP is the only user implemented configuration interface used, this signal should be tied Low (1'b0). This allows the MCAP access to the FPGA configuration logic as needed. |
| cap_gnt | Input | Active-High | Configuration Access Port arbitration grant signal. This signal should be used to arbitrate the use of the FPGA configuration logic between multiple user implemented configuration interfaces. If the MCAP is the only user implemented configuration interface used, this signal tied High (1'b1). This grants the MCAP access to the FPGA configuration logic upon request. |
| user_reset | Output | Active-High | Can be used to reset PCIe interfacing logic when the PCIe core is reset. Synchronized with user_clock. |
| user_clk | Output | N/A | Clock to be used by PCIe interfacing logic. |
| user_lnk_up | Output | Active-High | Identifies that the PCIe Express core is linked up with a host device. |
These signals can coordinate events in the user application, such as the release of
output 3-state buffers described in Tandem Configuration Details. Here is some
additional information about these signals:
-
mcap_design_switchis asserted after stage 2 is loaded. After stage 2 is loaded this output is controlled by the Root Port system. Whenever this signal is deasserted the PCIe solution IP is isolated from the rest of the user design and TLP BAR accesses return Unsupported Requests (URs). -
cap_req,cap_rel, andcap_gntsignals should be used to arbitrate the use of the FPGA configuration logic between multiple configuration interfaces such as the Internal Configuration Access Port (ICAP). The ICAP can be used as part of other IP cores or be instantiated directly in the user design. To arbitrate between the MCAP and the ICAP arbitration, logic must be created and use thecap_*signals to allow access to each interface as desired by the user design. The MCAP should always be granted exclusive access to the configuration logic until stage 2 is fully loaded. This is identified by the assertion of themcap_design_switchoutput. After the initial stage 2 design is loaded the MCAP interface can be used as desired by the system level design.cap_reqasserts when the Root Port connection requests access to the configuration logic. The user design can grant access by assertingcap_gntin response. The user design can then request that the MCAP release control of the configuration logic by asserting thecap_rel. The Root Port connection release control bydeasserting cap_req. The MCAP should not be accessed if the user logic does not assertcap_gnt. Similarly, other configuration interfaces should not attempt to access the configuration logic while access has been granted to the MCAP interface. -
user_resetcan likewise be used to reset any logic that communicates with the core when the core itself is reset. -
user_clkis simply the main internal clock for the PCIe IP core. Use this clock to synchronize any user logic that communicates directly with the core. -
user_lnk_up, as the name implies, indicates that the PCIe core is currently running with an established link.