Unsupported PCI Express Base Specification 4.0 Features (PCIE4C) - 1.3 English

UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213)

Document ID
PG213
Release Date
2023-10-19
Version
1.3 English

The following PCI Express Base Specification 4.0 Version 1.0 features are not supported by PCIe4C (UltraScale+ HBM):

  • Tag Scaling (10b Tag)
  • Feature DLLP, Flow Control Scaling
  • Retimer Present Bits
  • Lane Margining
  • Polling Compliance States, and Changes to Compliance Patterns
  • Link Extension Devices (Retimers)
Important: While the above limitations limit the ability to be 4.0 compliant, interoperation at 16.0 GT/s speeds is possible and works with the majority of 4.0 devices. Work with the vendor of the connected PCIe device to ensure that these limitations pose no issues. AMD conservatively guides system designers and system integrators to use slots / topologies / links which do not involve retimers where PCIe4C is used in systems designed to the PCI Express Base Specification Revision 4.0. AMD has not evaluated all possibilities of retimer implementations and applications across the permissible range of link topologies, link qualities, and link partners in system designs based on the PCI Express Base Specification Revision 4.0. This guidance pertains to retimers specifically but not redrivers, as redrivers are protocol-unaware.