BUFGGT RXUSRCLK Control (BUFGGT_RXUSRCLK_CTRL) Register (0x0154) - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

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2.2 English

BUFG_GT attributes register. For more details, see the UltraScale Architecture Clocking Resources User Guide (UG572).

Table 1. BUFGGT RXUSRCLK Control Register
Bit Default Value Access Type Description
0 0 RW CLR: Active-High asynchronous clear forcing BUFG_GT output to zero
3:1 0 RW DIV: Specifies the value to divide the clock. Divide value is value provided plus 1. For example, setting 3’b000 provides a divide value of 1 and 3’b111 is a divide value of 8.