Clock Placement - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

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2.2 English

For 7 series devices, you are expected to create package pin constraints for each instantiated transceiver differential reference clock buffer primitive as well as each instantiated differential recovered clock output buffer primitive, if used. The constraints reflect the transceiver primitive site locations.

Starting in Vivado 2018.3, the MGT reference clock frequency must be constrained at the Vivado Project top level XDC file at specified frequency; that is, for GTHE4: create_clock -period 6.400 [get_ports <NI-DRU REFCCLK portname>]