Connecting an UltraScale/ UltraScale+ GT South Reference Clock to a QPLL0/1 - 2.2 English

When a reference clock is used with QPLL0/1, the Video PHY Controller core opens four input ports, a GT channel clock, two common clocks, and a fabric clock (suffix odiv2). For example, SOUTHREFCLK0 is used with QPLL0/1, the core opens the following input ports:

gtsouthrefclk0

This port is the GT Channel clock and must be connected to the IBUF_OUT port of the IBUFDSGTE GT input clock buffer. See the following figure.

gtsouthrefclk00_in

This port is the QPLL0 clock and must be connected to the IBUF_OUT port of the IBUFDSGTE GT input clock buffer. See the following figure.

gtsouthrefclk01_in

This port is the QPLL1 clock and must be connected to the IBUF_OUT port of the IBUFDSGTE GT input clock buffer. See the following figure.

gtsouthrefclk0_odiv2_in

This port is the fabric clock and must be connected to the BUFG_GT_O port of the BUFG_GT buffer, which is being driven by the IBUF_DS_ODIV2 output of IBUFDSGTE GT input clock buffer. See the following figure.

Figure 1. South Reference Clock