The Video PHY Controller core is a feature-rich soft IP core incorporating all the necessary logic to properly interface with media access control (MAC) layers and perform physical-side interface (PHY) functionality. Xilinx® IP cores have been successfully tested on hardware and verified. For additional details on the interoperability results, contact your local Xilinx sales representative.
The PHY is intended to simplify the use of serial transceivers and adds domain-specific configurability. The Video PHY Controller IP is not intended to be used as a stand-alone IP and must be used with Xilinx Video MACs, such as the HDMI™ 1.4/2.0 Transmitter/Receiver Subsystems and DisplayPort TX/RX Subsystems . The core enables simpler connectivity between MAC layers for TX and RX paths. However, it is still important to understand the behavior, use, and any limitations of the transceivers. For more information, see UltraScale Architecture GTH Transceivers User Guide (UG576) and UltraScale Architecture GTY Transceivers User Guide (UG578).
The following figure shows the standard OSI Model and mapping it with video IP solutions.
In accordance with the OSI model, the major PHY component for video IP cores is SerDes. Standardizing the SerDes delivery model provides benefits and flexibility for a video MAC layer at the system level.
- AXI4-Lite interface to provide software access.
- AXI4-Stream-based GT channel interface for easier connectivity between different video link layers. (GT is also referred to as a serial transceiver.)