DisplayPort Receive - Status Path - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)
Document ID
PG230
Release Date
2023-11-03
Version
2.2 English

The following status is transferred to the Link layer. The status bits are driven using the AXI4-Lite clock.

Table 1. Receive Status Sideband Definition
Bit Position Status Details
0 Bank 0, GT Channel 0, RX Reset Done
1 Based on RXSYSCLKSEL[0], CPLL Channel 0/QPLL Lock is transferred
2 Bank 0, GT Channel 0, RX Byte Is Aligned output
3 Bank 0, GT Channel 1, RX Reset Done
4 Based on RXSYSCLKSEL[0], CPLL Channel 1/QPLL Lock is transferred
5 Bank 0, GT Channel 1, RX Byte Is Aligned output
6 Bank 0, GT Channel 2, RX Reset Done
7 Based on RXSYSCLKSEL[0], CPLL Channel 2/QPLL Lock is transferred
8 Bank 0, GT Channel 2, RX Byte Is Aligned output
9 Bank 0, GT Channel 3, RX Reset Done
10 Based on RXSYSCLKSEL[0], CPLL Channel 3/QPLL Lock is transferred
11 Bank 0, GT Channel 3, RX Byte Is Aligned output