Example Design - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

Document ID: PG230
Release Date: 2022-10-19
Version: 2.2 English

Introduction
Features
IP Facts
Overview
Core Overview
Applications
Unsupported Features
Licensing and Ordering
License Checkers
Product Specification
Performance
Resource Use
Port Descriptions
Clocking and Reset Interface Ports
GT Channels Interface Ports
Sideband Signals Interface Ports (Optional)
DisplayPort Transmit - Control Path
DisplayPort Transmit - Status Path
HDMI Transmit - Status Path
DisplayPort Receive - Control Path
DisplayPort Receive - Status Path
HDMI Receive - Status Path
AXI4-Lite Ports
Register Space
Version Register (0x0000)
Bank Select Register (BSR) (0x000C)
Shared Features and Reset Registers
Reference Clock Selection (RCS) Register (0x0010)
PLL Reset Register (PR) (0x0014)
PLL Lock Status (PLS) Register (0x0018)
PLL Reset (PR) Register (0x0014)
TX Initialization (TXI) Register (0x001C)
TX Initialization Status (TXIS) Register (0x0020)
RX Initialization (RXI) Register (0x0024)
RX Initialization Status (RXIS) Register (0x0028)
IBUFDS GTxx Control (IBUFDSGTxxCTRL) Register (0x002C)
Power Down Control (PDC) Register (0x0030)
Loopback Control (LBC) Register (0x0038)
Dynamic Reconfiguration Port (DRP) Registers
Dynamic Control Channel 1 (DRPCCH1) Register (0x0040)
Dynamic Control Channel 2 (DRPCCH2) Register (0x0044)
Dynamic Control Channel 3 (DRPCCH3) Register (0x0048)
Dynamic Control Channel 4 (DRPCCH4) Register (0x004C)
DRP Status Channel 1 (DRPSCH1) Register (0x0050)
DRP Status Channel 2 (DRPSCH2) Register (0x0054)
DRP Status Channel 3 (DRPSCH3) Register (0x0058)
DRP Status Channel 4 (DRPSCH4) Register (0x005C)
DRP Control Common (DRPCC) Register (0x0060)
DRP Status Common (DRPSC) Register (0x0064)
Transmitter Functions Registers
TX Control (TXC) Register (0x0070)
TX Buffer Bypass Control (TXBBC) Register (0x0074)
TX Status (TXS) Register (0x0078)
TX DRIVER Control – Channel 1 and 2 (TXDC12) Register (0x007C)
TX DRIVER Control – Channel 3 and 4 (TXDC34) Register (0x0080)
Receiver Functions
RX Control (RXC) Register (0x0100)
RX Status (RXS) Register (0x0104)
RX Equalization and CDR Register (0x0108)
RX TDLOCK VALUE Register (0x010C)
RX Symbol Error Counter – Channel 1 and 2 Register (0x0084)
RX Symbol Error Counter – Channel 3 and 4 Register (0x0088)
Interrupts Register
Interrupt Enable Register (IER) (0x0110)
Interrupt Disable Register (IDR) (0x0114)
Interrupt Mask Register (IMR) (0x0118)
Interrupt Status Register (ISR) (0x011C)
TXUSRCLK Clocking Registers
MMCM TXUSRCLK Control/Status (MMCM_TXUSRCLK_CTRL) Register (0x0120)
DRP CONTROL MMCM TXUSRCLK Register (0x0124)
DRP STATUS MMCM TXUSRCLK Register (0x0128)
BUFGGT TXUSRCLK Control (BUFGGT_TXUSRCLK_CTRL) Register (0x0134)
MISC TXUSRCLK Control (MISC_TXUSRCLK_CTRL) Register (0x0138)
MMCM RXUSRCLK Control/Status (MMCM_RXUSRCLK_CTRL) Register (0x0140)
DRP CONTROL MMCM RXUSRCLK Register (0x0144)
DRP STATUS MMCM RXUSRCLK Register (0x0148)
BUFGGT RXUSRCLK Control (BUFGGT_RXUSRCLK_CTRL) Register (0x0154)
MISC RXUSRCLK Control (MISC_RXUSRCLK_CTRL) Register (0x0158)
Clock Detector (HDMI) Registers
Clock Detector (HDMI) Control Register (0x0200)
Clock Detector (HDMI) Status Register (0x0204)
Clock Detector (HDMI) Frequency Counter Timeout Register (0x0208)
Clock Detector (HDMI) Transmitter Frequency Register (0x020C)
Clock Detector (HDMI) Receiver Frequency Register (0x0210)
Clock Detector (HDMI) Transmitter Timer Register (0x0214)
Clock Detector (HDMI) Receiver Timer Register (0x0218)
Clock Detector (HDMI) DRU Frequency Register (0x021C)
Data Recovery Unit Registers
Data Recovery Unit Control Register (0x0300)
Data Recovery Unit Status Register (0x0304)
Center Frequency Low Register – All Channels Register (0x0308)
Center Frequency High Register – All Channels Register (0x030C)
Gain Register – All Channels (0x0310)
TX TMDS Pattern Generator Control Register (0x0340)
Designing with the Core
Clocking
DisplayPort Clocking
GTXE2*/GTHE3 Clocking When Transmit Buffer Bypass is Disabled
GTXE2*/GTHE3 Clocking When Transmit Buffer Bypass is Enabled
HDMI Clocking
GTXE2
GTPE2
GTHE3, GTHE4, and GTYE4
Connecting an UltraScale/UltraScale+ GT NORTH Reference Clock to a CPLL
Connecting an UltraScale/ UltraScale+ GT South Reference Clock to a QPLL0/1
Using Fourth GT Channel as TX TMDS Clock Source
Resets
Interrupts
Program and Interrupt Flow
Video PHY DisplayPort TX Flow
Video PHY DisplayPort RX Flow
HDMI Program and Interrupt Flow
HDMI TX Flow
Video PHY Controller Core Driver TX Callbacks
HDMI RX Flow
Video PHY Controller Core Driver RX Callbacks
UltraScale GTHE3 and UltraScale+ GTHE4 and GTYE4 HDMI Implementation
CPLL Use
QPLL0 and QPLL1 Use
7 Series GTXE2 HDMI Implementation
7 Series GTPE2 HDMI Implementation
Design Flow Steps
Customizing and Generating the Core
DisplayPort Protocol with GTXE2 Transceivers
HDMI Protocol with GTPE2 and GTXE2 Transceivers
DisplayPort Protocol with GTHE3 and GTHE4 Transceiver
HDMI Protocol with GTHE4 and GTYE4 Transceivers
Parameter Description
User Parameters
Output Generation
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
HDMI Reference Clock Requirements
HDMI TX Oversampled Reference Clock Requirements
HDMI TX Clock Requirement Example
HDMI Generated Clocks
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement - DisplayPort
High-Speed I/O
I/O Standard and Placement - HDMI
TMDS Clock
High-Speed I/O
Board Design Guidelines - HDMI
Board Design Guidelines - DisplayPort
Simulation
Synthesis and Implementation
Example Design
HDMI Video PHY Controller Example Design
DisplayPort Video PHY Controller Example Design
Verification, Compliance, and Interoperability
Upgrading
Parameter Changes
Port Changes
Register Changes
Other Changes
Software Driver - Deprecated APIs
Debugging
Finding Help on Xilinx.com
Documentation
Known Issues
Answer Records
Master Answer Record for the Core
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
Interface Debug
AXI4-Lite Interfaces
AXI4-Stream Interfaces
HDMI Debugging
TX Only Sample Video PHY Controller Log
RX Only Sample Video PHY Controller Log
Passthrough Sample Video PHY Controller Log
Application Software Development
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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