GTHE3, GTHE4, and GTYE4 - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

Document ID
PG230
Release Date
2023-11-03
Version
2.2 English
Figure 1. GTHE3, GTHE4, and GTYE4
Figure 2. Video PHY Controller GTHE3, GTHE4 & GTYE4

The following parameters affect the clocking of GTHE3, GTHE4, and GTYE4 devices.

Adv_Clk_Mode
Configured through a check box in the Vivado IDE.

This controls where the IBUFDS_GTE3/4 clock buffers of MGTREFCLK0 and MGTREFCLK1 are placed. When disabled, IBUFDS_GTE3/4 is placed within the Video PHY Controller. When enabled, IBUFDS_GTE2 should be manually instantiated at the system level. This is an ideal mode for applications requiring reference clock sharing across multiple Video PHY Controller instances.

C_Rx_Tmds_Clk_Buffer
Configured through a Tcl command or through the Block Properties window in IP integrator. This controls the type of buffer to be used for driving the fabric associated with the RX TDMS output clock.

Valid parameters are: none, bufg, bufh, bufmr, and bufr.

C_Tx_Tmds_Clk_Buffer
Configured through a Tcl command or through the Block Properties window in IP integrator. This controls the type of buffer to be used for driving the fabric associated with theTX TMDS output clock.

Valid parameters are: none, bufg, bufh, bufmr, and bufr.

C_Tx_Video_Clk_Buffer
Configured through a Tcl command or through the Block Properties window in IP integrator. This controls the type of buffer to be used for driving the fabric associated with theTX Video output clock.

Valid parameters are: none, bufg, bufh, bufmr, and bufr.

C_Rx_Video_Clk_Buffer
Configured through a Tcl command or through the Block Properties window in IP integrator. This controls the type of buffer to be used for driving the fabric associated with theRX Video output clock.

Valid parameters are: none, bufg, bufh, bufmr, and bufr.

C_Use_Oddr_for_Tmds_Clkout
Configured through a Tcl command or through the Block Properties window in IP integrator. This controls whether an ODDRE1 is inserted to drive the OBUFTDS for differential TX and RX TMDS output clocks.

Valid parameters are: TRUE or FALSE.

Note: The BUFG_GTs that are directly connected to the transceiver are a hard requirement for clocks that are either driving or being driven by the GTHE3, GTHE4, and GTYE4 transceivers. They cannot be disabled or removed from the RTL.