GTXE2*/GTHE3 Clocking When Transmit Buffer Bypass is Enabled - 2.2 English

For DisplayPort 1.2, connect the DP159 forwarded clock to any of the reference clock inputs and use a valid reference clock selection through the driver API.

For DisplayPort 1.4, connect a 270 MHz clock to any of the reference clock inputs and use a valid reference clock selection using the driver API. In DisplayPort 1.4, the Retimer forwarded clock is not used.

The txoutclk_out/rxoutclk_out signals are connected to the DisplayPort MAC controller. In TX buffer bypass mode, the MMCM clocking resource is used on the TX path and you have to program valid divider/multiplier values using the driver API.

Figure 1. GTXE2/GTHE3/GTHE4 Clocking (TX Buffer Bypass = Enabled)

The system clock must drive the vid_phy_sb_aclk, vid_phy_axi4lite_aclk, and drpclk (for UltraScale+/UltraScale devices only). The ports should be connected to a valid clock, for example, 50 MHz, 100 MHz, or 150 MHz. The system clock must have sufficient buffer, for example, BUFG, before it can be used and connected.