HDMI Debugging - 2.2 English

1. Make sure that the HDMI cable is properly inserted.
2. Ensure that the correct GTREFCLK input pins are connected according to Customizing and Generating the Core.
3. Ensure that cable detect and HPD pins are properly connected with the correct active level setting in the HDMI TX or RX subsystem GUI.
4. Try connecting with a different cable.

This is a known limitation of bonded mode.

While on bonded mode, resolutions that require DRU cannot be transmitted by the Video PHY Controller because TX is being clocked by the DRU REFCLK (125 MHz). The TX REFCLK must run at TX TMDS clock * Oversampling Factor to properly transmitted low resolutions.

1. Check the RCS register and ensure the clock selections are done correctly.
2. Check the GT initialization sequence after configuration.

   For example, GTH GTTXRESET should be held HIGH until PLL_LOCK is asserted. Failing to do so might cause the PLL and GT to get stuck. See the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476), UltraScale Architecture GTH Transceivers User Guide (UG576), and 7 Series FPGAs GTP Transceivers User Guide (UG482) for more information.

3. Ensure the GTREFCLK is present and is driving the PLL.
4. Try toggling the PLL_GT_RESET bits of TXI or RXI registers.
5. Ensure that the Video PHY Controller driver and IP versions are from the same Vivado build.

This indicates that the HDMI design received a video carrying a TMDS Clock that is below the PLL thresholds and there is no NI-DRU in the Video PHY Controller instance to receive it.

The DRU must be enabled from the Video PHY Controller GUI to be able to receive resolutions below the PLL threshold. The DRU must be supplemented with a corresponding GT clock based on the requirements listed in Video PHY Controller HDMI Reference Clock Requirements (link below).

This happens when the clock detector module identifies a mismatch between the actual and required DRU REFCLK frequency. This can be due to two reasons:

• The DRU clock frequency is outside ±10 kHz tolerance of the required frequency.
• When the DRU Ref lock Selection is the same as the RX or TX Ref Clock Selection, disabling the RX or TX Ref Clock Selection can also disable the DRU Ref Clock, which reports the DRU clock frequency as equal to 1 Hz.

Switch to CPLL bonded mode when transmitting or receiving videos that fall into QPLL holes.

Switch out of bonded mode when operating in Passthrough mode and receiving DRU line rate.

You can add functions inside the VphyProcessError API of xhdmi_example.c to automatically switch in and out of bonded mode depending on the error type.

PLL holes are generally a limitation of GTXE2 QPLL when the TMDS clock of a video format falls outside the supported range of the QPLL. Details of the QPLL hole discussion can be found in the 7 series GTXE2 Video PHY Controller core HDMI Implementation section.