The Video PHY Controller IP generates the TX TMDS, link, and video clocks that the HDMI 1.4/2.0 Transmitter Subsystem requires. See the Clocking section of the HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235) for more information.
The Video PHY Controller IP generates the RX link and video clocks that the HDMI 1.4/2.0 Receiver Subsystem requires. See the Clocking section of the HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236) for more information.