The following status is transferred to the Link layer. The status bits are driven using the AXI4-Lite clock.
| Bit Position | Status Details |
|---|---|
| 0 | RX Link Ready. This signal is asserted to indicate that the GT RX initialization is completed (rxresetdone). |
| 1 | RX Video Ready. This signal is asserted to indicate that the video clock from the RX MMCM/PLL block is stable. |
| [7:2] | Reserved. |