HDMI TX Clock Requirement Example - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

Document ID
PG230
Release Date
2023-11-03
Version
2.2 English

The frequency range of the external programmable clock generator must be selected based on the transceiver type and the PLL type for TX. The following table shows the frequency range needed from the clock generator if the Video PHY Controller is used to support all the video formats in the tables in the Video PHY Controller HDMI Implementation section.

Table 1. External Clock Generator Typical Frequency Range
Configuration TX PLL Reference Clock Range (MHz)
GTHE3/GTHE4/GTYE4 CPLL 50 to 297
QPLL0 61.25 to 297
GTXE2 CPLL 80 to 297
QPLL 74.125 to 297
GTPE2 PLL0/1 80 to 297

The following table shows the external clock generator frequency range if the Video PHY Controller TX is used to support video formats of SMPTE-SDI: SD-SDI, HD-SDI, and 3G-SDI, which in HDMI have equivalent TMDS clocks 27, 74.25, or 74.25/1.001 MHz and 148.5 or 148.5/1.001 MHz, respectively. SD-SDI reference clock is below the minimum threshold of all PLL types. Thus, the oversampling mode must be used to support it. HD-SDI reference clock is below the minimum threshold of the GTHE3/GTHE4/GTYE4, GTXE2 CPLL, and GTPE2 PLL0/1, thus oversampling mode must be used to support it for the corresponding GT and PLL types.

Table 2. External Clock Generator Frequency Range for SMPTE-SDI
Transceiver Type TX PLL Reference Clock Range (MHz) Remarks
GTHE3/GTHE4/GTYE4 CPLL 135 to 222.75

SD-SDI uses x5 oversampling

HD-SDI uses x3 oversampling

QPLL0 74.25/1.001 to 148.5 SD-SDI uses x3 oversampling
GTXE2 CPLL 81 to 222.75

SD-SDI uses x3 oversampling

HD-SDI uses x3 oversampling

QPLL 74.25/1.001 to 148.5 SD-SDI uses x3 oversampling
GTPE2 PLL0/1 81 to 222.75

SD-SDI uses x3 oversampling

HD-SDI uses x3 oversampling