In normal cases, the GT reference clock requirement is equal to the TMDS clock requirement of a given HDMI resolution.
HdmiTxRefClkHzvariable in the Video PHY Controller data structure declared in the application (for example, in reference design:
HdmiTxRefClkHzvalue is valid and can be accessed any time after TX Alignment Done Interrupt occurs (see the Video PHY Controller HDMI TX Flow). This value is ideally used in programming the external clock generator frequencies for GT TX operation.
The Video PHY Controller HDMI TX application enters the oversampling mode when the reference clock required by video resolution to be transmitted is below the HDMI PLL minimum frequency. The Video PHY Controller driver increases the reference clock by a factor of x3 or x5 until the minimum frequency for PLL is met. The following table shows the minimum reference clock per transceiver and PLL types.
For example, the GTHE3 CPLL needs to transmit 480p 60 Hz at eight bits per component. This video format requires a TMDS clock of 27 MHz which is below the GTHE3 CPLL 50 MHz minimum clock. The Video PHY Controller driver searches for the oversampling factor that satisfies this condition, which is x3. The new GT reference clock requirement is 81 MHz.
|Transceiver Type||PLL Type||HDMI Min Reference Clock (MHz)|