IP Facts - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)
Document ID
PG230
Release Date
2022-10-19
Version
2.2 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1

HDMI Video PHY Controller:

  • UltraScale+™ families (GTHE4, GTYE4) 2
  • UltraScale™ families (GTHE3)
  • Zynq®-7000 SoC (GTXE2)
  • 7 series (GTXE2)
  • Artix-7 (GTPE2) 7

DisplayPort Video PHY Controller:

  • UltraScale+™ families (GTHE4, GTYE4) 2
  • UltraScale™ families (GTHE3)
  • Zynq®-7000 SoC (GTXE2)
  • Virtex®-7 (GTXE2)
  • Kintex®-7 (GTXE2) 3
Supported User Interfaces AXI4-Stream, AXI4-Lite
Resources Performance and Resource Use web page
Provided with Core
Design Files Verilog
Example Design Provided with the HDMI and Display Port IP cores. 4
Test Bench Not Provided
Constraints File Xilinx Design Constraints (XDC)
Simulation Model Not Provided
Supported S/W Driver 5 Standalone, Linux (HDMI Only)
Tested Design Flows 6
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 57842
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.

  2. The maximum line rate for DisplayPort is 2.7 Gb/s for GTHE4/GTYE4 Zynq® UltraScale+™ MPSoC and UltraScale+™ family -1LI (0.72 V) devices operated at 16-bit or 20-bit internal datapath.

    The maximum line rate for DisplayPort is 5.4 Gb/s for GTHE4/ GTYE4 Zynq® UltraScale+™ MPSoC, UltraScale+™ and GTHE3/ GTYE3 Zynq® UltraScale+™ MPSoC and UltraScale™ family -2LE (0.72 V), -1E,-1I, and -1LI (0.85 V) devices.

  3. For Kintex-7: QPLL1/2 does not cover all DP line rate ranges. Using the CPLL for TX path is recommended.
  4. See the HDMI and DisplayPort documentation references in References.

  5. Standalone driver details can be found in <install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers_api_toc.htm.

  6. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide .
  7. GTPE2 -1, -1L, and -2LE (0.9V) parts are not supported by the Video PHY Controller. Artix -2 and -3 are limited to HDMI1.4 data rates due to fabric performance limitations.