Parameter Description - 2.2 English

The Vivado IDE displays a representation of the IP symbol on the left side, and the parameter assignments on the right side, which are described as follows:

Component Name

The component name is used as the base name of the output files generated for the module. Names must begin with a letter and must be composed of characters: a to z, 0 to 9, and "_". The name vid_phy_controller cannot be used as a component name.

Transceiver

Specifies the types of transceivers that are used in this core. This option is not editable and depends on the FPGA family. The possible types are GTPE2, GTXE2, GTHE3, GTHE4, and GTYE4.

Transceiver Width

Specifies the width of the transceiver that is used in this core.

TX/RX Protocol Selection

Specifies the protocol that is supported under this core. Two protocols are currently available: DisplayPort and HDMI™ (High-Definition Multimedia Interface). Mixed protocols is not supported for both transmitter and receiver (that is, transceiver protocol is HDMI and receiver protocol is DisplayPort, and vice-versa).

Note: When TX/RX Protocol Selection is set to None, some of the options such as PLL type and Ref Clock Selection are still open for changes and vary per protocol of opposite direction. These options can be ignored when TX/RX Protocol Selection is set to None. For HDMI, it is important to note that the GT COMMON is optimized out of the Video PHY Controller when QPLL or QPLL0/1 is not associated with either the TX or the RX. This means that for GTXE2, dynamic switching from CPLL to QPLL is not possible when QPLL is optimized out from the design. Consider the following scenarios as examples:

• GTHE3 with TX is DisplayPort and RX is None.
  • The only configurable option on RX is RX Ref Clock Selection but this has no impact because both refclk ports are open for TX usage regardless of the setting in RX Ref Clock Selection.
• GTHE3 with TX is HDMI and RX is None.
  • The only configurable options on RX are RX PLL Type and RX Ref Clock Selection.
  • There is an automatic checking on the PLL Type that disables the setting of the same PLL type for TX and RX.
  • For RX Ref Clock Selection, the setting has no impact on the refclk port.

TX/RX Clock Primitive

Specifies the clock primitive for TX/RX. Valid values are MMCM and PLL.

Note: PLL option is only enabled when TX/RX Protocol is HDMI and Transceiver is GTHE4 or GTYE4.

TX/RX Max GT Line Rate

Specifies the maximum line rate for the transceiver. For HDMI protocol, this option is fixed to 5.94 Gbps.

TX/RX Channel

Specifies the number of transceiver channels to be generated in this core. For DisplayPort protocol, this option is allowed to have one, two, or four channels. For HDMI protocol, this option is fixed to three channels only.

TX/RX Ref Clock Selection

Specifies the reference clock that corresponds to the transceiver.

TX Buffer Bypass

When checked, the TX buffer is excluded from the core.

TX REFCLK Ready Active

Specifies active-Low/High for TX RefClk Ready. This option is displayed when HDMI protocol is selected.

Use Fourth GT Channel as TX TMDS Clock

To enable/disable the function specified as per the display option. This option is displayed when HDMI protocol is selected.

Ni-DRU

When checked, the NI-DRU is included in the core. This option is displayed when HDMI protocol is selected for the receiver.

Ni-DRU Ref Clock Selection

Specifies the reference clock that corresponds to the NI-DRU. This option is displayed when HDMI protocol is selected for the receiver.

Important: There is no automatic check between the DRU Ref Clock and the RX/TX Ref Clock Selection. Therefore, you should avoid using the same clock for the DRU Ref Clock as either the TX or RX PLL Ref Clock.

Number of pixels per clock

Specifies the number of pixels for video clock generation. (Option is displayed when HDMI protocol is selected.)

Advanced Clock Mode

When checked under DisplayPort protocol, the core exposes all the available single-ended clock ports (for example, gtnorth/southrefclk_0/1 ports are revealed for GTXE2, GTHE3, GTHE4). When checked under HDMI protocol, the core exposes its active/selected single-ended clock ports and additional odiv_2 (only applicable for GTXE3 and GTHE4) clock ports. If unchecked, the core only exposes its active/selected differential clock ports.

DRP Clock Frequency (MHz)

Specifies the frequency that needs to be driven at the DRP clock. This option is displayed with a fixed value when the AMD UltraScale™ transceiver is selected.

GT

Starting Channel Location specifies the starting channel location that aligns with the Quad boundary. This option is displayed when AMD UltraScale™ transceiver is selected.

GT Bank <num>

Indicates the transceiver bank location. This option Indicator is displayed when UltraScale transceiver is selected.