Power Down Control (PDC) Register (0x0030) - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)
Document ID
PG230
Release Date
2022-10-19
Version
2.2 English
Table 1. Power Down Control (PDC) Register
Bit Default Value Access Type Description
Channel 1
0 0 RW CPLLPD 1
1 0 RW QPLL0PD/PLL0PD
2 0 RW QPLL1PD (For UltraScale and UltraScale+ devices)/PLL1PD
4:3 0 RW RXPD[1:0]
6:5 0 RW TXPD[1:0]
7 N/A N/A Reserved
Channel 2
8 0 RW CPLLPD 1
10:9 N/A N/A Reserved
12:11 0 RW RXPD[1:0]
14:13 0 RW TXPD[1:0]
15 N/A N/A Reserved
Channel 3
16 0 RW CPLLPD 1
18:17 N/A N/A Reserved
20:19 0 RW RXPD[1:0]
22:21 0 RW TXPD[1:0]
23 N/A N/A Reserved
Channel 4
24 0 RW CPLLPD 1
26:25 N/A N/A Reserved
28:27 0 RW RXPD[1:0]
30:29 0 RW TXPD[1:0]
31 N/A N/A Reserved
  1. This field is applicable only for 7 series devices. For UltraScale and UltraScale+ devices, CPLLPD is handled by the GT wizard FSMs internally.