Product Specification - 2.2 English

The Video PHY Controller core is the supported method of configuring and using transceivers with MAC subsystems. The core simplifies serial transceiver (GT) use by providing a standardized interface and software programmability of serial transceiver functions.

The functional block diagram of the core is shown in the following figure.

Figure 1. Video PHY Controller Core Block Diagram

PHY Control/Status Manager

This block manages AXI4-Lite bus protocol accesses and handles memory map accesses and interrupt management.

DRP Controller

This block controls the handshake between AXI4-Lite access and GT DRP and MMCM/PLL access. For example, this block latches DRP_RDY and holds it until a read from AXI4-Lite is done. After a proper RDY handshake, a new dynamic reconfiguration port (DRP) transaction can be initiated.

User Clock Source

This block has the GT input clock buffers and generates USRCLK and USRCLK2 for GTs. In cases where the TX buffer is bypassed, a mixed-mode clock manager (MMCM)/a phase-locked loop (PLL) generates the required output clocks based on TX/RXOUTCLK. In HDMI, along with generating USRCLK and USRCLK2, this block also produces video clocks and differential and single-ended TX Transition Minimized Differential Signaling (TMDS) CLK as per the requirement of the HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235) and HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236). It also buffers the RX TMDS CLK and forwards it as differential and single-ended clocks for generic use.

Note: The video clock maximum frequency is 297 MHz across all transceiver types except GTPE2, which is maxed at 148.5 MHz. This means GTPE2 cannot support video formats with video clocks > 148.5 MHz. For more information on HDMI clocking requirements, see the Clocking sections of the HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235) and the HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236).

GT Common

This block controls the COMMON primitive of the serial transceiver. It has external PLL management and DRP access. This block is available as part of the PHY top level in 7 series devices. For AMD UltraScale™ devices, this block is part of the GT wizard core.

AXI4-Stream Mapper

This block/logic maps the GT input or output data according to the AXI4-Stream protocol defined in the GT specification.

NI-DRU

This block is used in applications where lower line rates (those below the rates supported by the respective GTs) are needed. In HDMI™ , the NI-DRU is enabled when the RX TMDS clock is below the threshold of the specific GT type.

• GTXE2 Thresholds
  • QPLL = 74.125 MHz
  • CPLL = 80.000 MHz
• GTPE2 Thresholds
  • PLL0/1 = 80.000 MHz
• GTHE3, GTHE4, and GTYE4 Thresholds:
  • QPLL0 = 61.250 MHz
  • CPLL = 50.00 MHz

Note: QPLL1 is not used in NI-DRU mode.

NI-DRU requires an additional fixed reference clock to the GT RX on top of the RX TMDS clock to run the low line rate data recovery. For more information on the reference clock frequency requirement per transceiver type, see HDMI Reference Clock Requirements.

TMDS Clock Pattern Generator

This block is enabled when the Use fourth GT Channel as TX TMDS clock option is enabled. It connects to the fourth GT channel and provides the pattern to transmit the TMDS clock through the GT channel.