When using the two Quad PLL (QPLL) types for the HDMI transmitter and receiver, line rate restrictions are introduced due to the VCO range and limited set of multipliers of the QPLL. The Video PHY Controller core driver dynamically switches between QPLL0 and QPLL1 to overcome these restrictions with QPLL0 having the priority if the TMDS clock frequency falls within the valid range of QPLL0 and QPLL1. For the transmitter, the Video PHY Controller core driver uses oversampling and the dynamic QPLL switching to work around the QPLL limitations.
When the GT driver detects that the TMDS clock frequency is less than 61.25 MHz, it enables the NI-DRU to receive these lower bit rates that are less than 0.6125 Gb/s. The NI-DRU runs at 2.5 Gb/s, which enables it to recover line rates that cannot be supported by the QPLL0. The Video PHY Controller does not use QPLL1 in NI-DRU mode.
The VCO of the QPLL0 must run in the frequency range of 9.8 GHz to 16.375 GHz. The QPLL0 can apply multipliers of 20, 40, 80, or 160 to the TMDS clock.
The following table shows how the TMDS clock frequency interacts with the QPLL0 and the frequency ranges that can be supported.
|TMDS Clock Frequency (MHz)||QPLL0 Multiplier||Notes|
TX: Line Rate Dependent
RX: NI-DRU is used
|61.25 to 102.34375||160||Supported|
|102.34375 to 122.5||–||TMDS clock range cannot be supported|
|122.5 to 204.6875||80||Supported|
|204.6875 to 245||–||TMDS clock range cannot be supported|
|245 to 409.375||40||Supported|
|409.375 to 490||–||TMDS clock range cannot be supported|
If the QPLL0 is used as the clock source, video formats with a TMDS clock of 102.34375 MHz to 122.5 MHz, 204.6875 MHz to 245 MHz, and frequencies higher than 409.375 MHz cannot be supported because a multiplier cannot be used to meet the valid VCO range.
The VCO of the QPLL1 must run in the frequency range of 8.0 GHz to 13.0 GHz. The QPLL1 can apply multipliers of 20, 40, 80, or 160 to the TMDS clock.
The following table shows how the TMDS clock frequency interacts with the QPLL1 and the frequency ranges that can be supported.
If the QPLL1 is used as the clock source, video formats with a TMDS clock of 81.25 MHz to 100 MHz, 162.5 MHz to 200 MHz, and 325 MHz to 400 MHz cannot be received because a multiplier cannot be used to meet the valid VCO range.
|TMDS Clock Frequency (MHz)||QPLL1 Multiplier||Notes|
RX: NI-DRU is used
|50.0 to 81.25||160||Supported|
|81.25 to 100||–||TMDS clock range cannot be supported|
|100 to 162.5||80||Supported|
|162.5 to 200||–||TMDS clock range cannot be supported|
|200 to 325||40||Supported|
|325 to 400||–||TMDS clock range cannot be supported|
|400 to 650||20||Supported|
The following table is for illustration only. For unlisted color formats, support might be possible if they are not restricted by the VCO frequency range.
|Resolution (Hz)||Bits Per Pixel|
|WXGA + 60||√||√||√||√|