| Bit | Default Value | Access Type | Description |
|---|---|---|---|
| 3:0 | 0 | RW | QPLL (GTXE2) / QPLL0REFCLKSEL (GTHE3/GTHE4/GTYE4) / PLL0REFCLKSEL (GTPE2) |
| 7:4 | 0 | RW | CPLLREFCLKSEL |
| 11:8 | 0 | RW | QPLL1REFCLKSEL (For UltraScale/UltraScale+ devices)/PLL1REFCLKSEL (GTPE2) |
| 23:12 | 0 | RW | Reserved |
| 27:24 | 0 | RW | {TXSYSCLKSEL[1:0], RXSYSCLKSEL[1:0]} |
| 31:28 | 0 | RW | {TXPLLCLKSEL[1:0], RXPLLCLKSEL[1:0]} For UltraScale and UltraScale+ devices |