Sideband Signals Interface Ports (Optional) - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

Document ID
PG230
Release Date
2023-11-03
Version
2.2 English
Table 1. Sideband Signals Optional Ports
Name 1 I/O Description
vid_phy_control_sb_tx_tready O AXI4-Stream based tready indicator
vid_phy_control_sb_tx_tdata I AXI4-Stream based tdata bus

Not used by the DisplayPort Protocol

vid_phy_control_sb_tx_tvalid I AXI4-Stream based tvalid
vid_phy_status_sb_tx_tready I AXI4-Stream based tready indicator
vid_phy_status_sb_tx_tdata[7:0] O

AXI4-Stream based tdata bus

For DisplayPort, see DisplayPort Transmit - Status Path.

For HDMI™ , see HDMI Transmit - Status Path.

vid_phy_status_sb_tx_tvalid O AXI4-Stream based tvalid
vid_phy_control_sb_rx_tready O AXI4-Stream based tready indicator
vid_phy_control_sb_rx_tdata[7:0] (DisplayPort Only) I AXI4-Stream based tdata bus.

For DisplayPort, see DisplayPort Receive - Control Path.

vid_phy_control_sb_rx_tvalid (DisplayPort Only) I AXI4-Stream based tvalid
vid_phy_status_sb_rx_tready (DisplayPort Only) I AXI4-Stream based tready indicator
vid_phy_status_sb_rx_tdata{15:0] (DisplayPort)

vid_phy_status_sb_rx_tdata[7:0] (HDMI)

O

AXI4-Stream based tdata bus.

For DisplayPort, see DisplayPort Receive - Status Path. For HDMI, see HDMI Receive - Status Path.

vid_phy_status_sb_rx_tvalid O AXI4-Stream based tvalid
  1. Clock Domain: Sideband clock.