TX Control (TXC) Register (0x0070) - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)
Document ID
PG230
Release Date
2023-11-03
Version
2.2 English
Table 1. TX Control (TXC) Register
Bit Default Value Access Type Description
Channel 1
0 0 RW TX8B10BEN 1
1 0 RW TXPOLARITY (0: Not-inverted 1: Inverted)
4:2 0 RW TXPRBSSEL[2:0]
7 series PRBS modes:
  • 000 - Standard operation
  • 001 - PRBS-7
  • 010 - PRBS-15
  • 011 - PRBS-23
  • 100 - PRBS-31
UltraScale /UltraScale+ PRBS modes:
  • 000 - Standard operation
  • 001 - PRBS-7
  • 010 - PRBS-9
  • 010 - PRBS-15
  • 011 - PRBS-23
  • 100 - PRBS-31
5 0 RW TXPRBSFORCEERR
6 0 RW TXPRBSSEL 2
7 0 RW Reserved
Channel 2
8 0 RW TX8B10BEN 1
9 0 RW TXPOLARITY (0: Not-inverted 1: Inverted)
12:10 0 RW TXPRBSSEL[2:0]. Refer to Channel 1 for PRBS modes.
13 0 RW TXPRBSFORCEERR
14 0 RW TXPRBSSEL 2
15 0 RW Reserved
Channel 3
16 0 RW TX8B10BEN 1
17 0 RW TXPOLARITY (0: Not-inverted 1: Inverted)
20:18 0 RW TXPRBSSEL[2:0]. Refer to Channel 1 for PRBS modes.
21 0   TXPRBSFORCEERR
22 0 RW TXPRBSSEL 2
23 0 RW Reserved
Channel 4
24 0 RW TX8B10BEN 1
25 0 RW TXPOLARITY (0: Not-inverted 1: Inverted)
28:26 0 RW TXPRBSSEL[2:0]. Refer to Channel 1 for PRBS modes.
29 0 RW TXPRBSFORCEERR
30 0 RW TXPRBSSEL 2
31 0 RW Reserved
  1. For the HDMI protocol, this register field is unused.
  2. For the DisplayPort protocol, RXDFELPMRESET is an unused field.