The GTHE3 transceiver in the UltraScale™ FPGAs and the GTHE4 and GTYE4 transceivers in the UltraScale+™ FPGAs have three types of PLLs, the QPLL0, QPLL1, and the CPLL . The QPLL0 and QPLL1 are shared by all four transceivers in the Quad. Each transceiver has its own CPLL. The Video PHY Controller core uses all of the PLL types to support transmitter and receiver operations simultaneously. The Video PHY Controller core allows you to choose whether the QPLL0/1 or the CPLL is used by the transmitter. The receiver should use the other PLL that is not used by the TX.
Using the CPLL for the HDMI receiver includes certain restrictions. The TX does not have these restrictions because the GT driver uses oversampling techniques to work around the limitations of the CPLL. The HDMI RX limitations for the CPLL are described in this section.
The CPLL voltage controlled oscillator (VCO) must run in the range of 2.0 GHz to 6.25 GHz. The VCO frequency is dependent on the TMDS clock frequency. The CPLL can apply a limited set of multipliers to the TMDS clock frequency. The GT driver measures the TMDS clock frequency and attempts to find a valid multiplier that results in a VCO frequency that is within the allowed range.