Table: AXI4-Lite Control Interface
shows the AXI4-Lite control interface signals. This interface runs at the
aclk_ctrl
clock. Control of the video processing pipe is only supported through the Video Processing Subsystem driver. Data-width is automatically configured based on the PPC of the design.
Note:
Control of the video processing pipe is only supported through the video processing subsystem driver. The register map is provided for debug purposes only.
Table 2-8:
AXI4-Lite Control Interface
|
Name
|
Direction
|
Width
|
Description
|
|
s_axi_ctrl_awaddr
|
In
|
20
|
Write address
|
|
s_axi_ctrl_awprot
|
In
|
3
|
Write address protection
|
|
s_axi_ctrl_awvalid
|
In
|
1
|
Write address valid
|
|
s_axi_ctrl_awready
|
Out
|
1
|
Write address ready
|
|
s_axi_ctrl_wdata
|
In
|
32
|
Write data
|
|
s_axi_ctrl_wstrb
|
In
|
4
|
Write data strobe
|
|
s_axi_ctrl_wvalid
|
In
|
1
|
Write data valid
|
|
s_axi_ctrl_wready
|
Out
|
1
|
Write data ready
|
|
s_axi_ctrl_bresp
|
Out
|
2
|
Write response
|
|
s_axi_ctrl_bvalid
|
Out
|
1
|
Write response valid
|
|
s_axi_ctrl_bready
|
In
|
1
|
Write response ready
|
|
s_axi_ctrl_araddr
|
In
|
20
|
Read address
|
|
s_axi_ctrl_arprot
|
In
|
3
|
Read address protection
|
|
s_axi_ctrl_arvalid
|
In
|
1
|
Read address valid
|
|
s_axi_ctrl_aready
|
Out
|
1
|
Read address ready
|
|
s_axi_ctrl_rdata
|
Out
|
32
|
Read data
|
|
s_axi_ctrl_rresp
|
Out
|
2
|
Read data response
|
|
s_axi_ctrl_rvalid
|
Out
|
1
|
Read data valid
|
|
s_axi_ctrl_rready
|
In
|
1
|
Read data ready
|