AXI4-Stream Video - 2.4 English

The Video Processing Subsystem has AXI4-Stream video input and output interfaces named s_axis and m_axis , respectively. These interfaces follow the interface specification as defined in the Video IP chapter of the Vivado AXI Reference Guide (UG1037) [Ref 9] . The video AXI4-Stream interface can be single, dual, quad, or octa pixels per clock and can support 8, 10, 12, or 16 bits per component. For example, the pixel mapping per color format and bus signals for 10 bits per component are shown in Table: Dual Pixels per Clock, 10 Bits per Component Mapping for RGB through Table: Dual Pixels per Clock, 10 Bits per Component Mapping for YUV 4:2:0, for Odd Lines .

Table 2-2: Dual Pixels per Clock, 10 Bits per Component Mapping for RGB
63:60	59:50	49:40	39:30	29:20	19:10	9:0
zero padding	R1	B1	G1	R0	B0	G0

Table 2-3: Dual Pixels per Clock, 10 Bits per Component Mapping for YUV 4:4:4
63:60	59:50	49:40	39:30	29:20	19:10	9:0
zero padding	V1	U1	Y1	V0	U0	Y0

Table 2-4: Dual Pixels per Clock, 10 Bits per Component Mapping for YUV 4:2:2
63:60	59:50	49:40	39:30	29:20	19:10	9:0
zero padding	zero padding	zero padding	V0	Y1	U0	Y0

Table 2-5: Dual Pixels per Clock, 10 Bits per Component Mapping for YUV 4:2:0, for Even Lines
63:60	59:50	49:40	39:30	29:20	19:10	9:0
zero padding	zero padding	zero padding	V0	Y1	U0	Y0

Table 2-6: Dual Pixels per Clock, 10 Bits per Component Mapping for YUV 4:2:0, for Odd Lines
63:60	59:50	49:40	39:30	29:20	19:10	9:0
zero padding	zero padding	zero padding	zero padding	Y1	zero padding	Y0

This IP always generates three video components even if the video format is set to be YUV 4:2:0 or YUV 4:2:2 at run-time. The unused components can be set to zero. All video streaming interfaces follow the interface specification as defined in the AXI4-Stream Video IP and System Design Guide (UG934 ) [Ref 8] .

Table: AXI4-Stream Interface Signals shows the interface signals for input and output AXI4-Stream video streaming interfaces.

Table 2-7: AXI4-Stream Interface Signals
Name	Direction	Width	Description
s_axis_tdata	In	floor(((3 x bits_per_component x pixels_per_clock) + 7) / 8) x 8	Input Data
s_axis_tready	Out	1	Input Ready
s_axis_tvalid	In	1	Input Valid
s_axis_tid	In	1	Input data stream identifier
s_axis_tdest	In	1	Input data routing identifier
s_axis_tkeep	In	(s_axis_video_tdata width)/8	Input byte qualifier that indicates whether the content of the associated byte of TDATA is processed as part of the data stream
s_axis_tlast	In	1	Input End of Line
s_axis_tstrb	In	(s_axis_video_tdata width)/8	Input byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte
s_axis_tuser	In	1	Input Start of frame
m_axis_tdata	Out	floor(((3 x bits_per_component x pixels_per_clock) + 7) / 8) x 8	Output Data
m_axis_tdest	Out	1	Output data routing identifier
m_axis_tid	Out	1	Output data stream identifier
m_axis_tkeep	Out	(m_axis_video_tdata width)/8	Output byte qualifier that indicates whether the content of the associated byte of TDATA is processed as part of the data stream
m_axis_tlast	Out	1	Output End of Line
m_axis_tready	In	1	Output Ready
m_axis_tstrb	Out	(m_axis_video_tdata width)/8	Output byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte
m_axis_tuser	Out	1	Output Start of frame
m_axis_tvalid	Out	1	Output Valid

Both video streaming interfaces run at the video stream clock speed aclk_axis .