The following table provides the register map of deinterlacer registers in video processing subsystem.
|
Register |
Description |
|---|---|
|
0x000 |
Control signals • bit 0 - ap_start (Read/Write/COH) • bit 1 - ap_done (Read/COR) • bit 2 - ap_idle (Read) • bit 3 - ap_ready (Read) • bit 7 - auto_restart (Read/Write) • Others - reserved |
|
0x004 |
Global Interrupt Enable Register • bit 0 - Global Interrupt Enable (Read/Write) • Others - reserved |
|
0x008 |
IP Interrupt Enable Register (Read/Write) • bit 0 - Channel 0 (ap_done) • bit 1 - Channel 1 (ap_ready) • Others - reserved |
|
0x00c |
IP Interrupt Status Register (Read/TOW) • bit 0 - Channel 0 (ap_done) • bit 1 - Channel 1 (ap_ready) • Others - reserved |
|
0x010 |
Width • bit 15~0 - HwReg_width[15:0] (Read/Write) • Others - reserved |
|
0x014 |
Reserved |
|
0x018 |
Height • bit 15~0 - HwReg_height[15:0] (Read/Write) • Others - reserved |
|
0x01c |
Reserved |
|
0x020 |
Read Frame Buffer • bit 31~0 - read_fb[31:0] (Read/Write) |
|
0x024 |
Read Frame Buffer • bit 31~0 - read_fb[63:32] (Read/Write) |
|
0x028 |
Reserved |
|
0x030 |
Color Format • bit 7~0 - colorFormat[7:0] (Read/Write) • Others - reserved |
|
0x034 |
Reserved |
|
0x038 |
Algorithm • bit 7~0 - algo[7:0] (Read/Write) ° 0x00 - median algorithm ° 0x01 - bob algorithm ° 0x02 - weave algorithm ° 0x03 - vertical temporal linear interpolation algorithm ° 0x05 - reserved ° 0x06 - pass through • Others - reserved |
|
0x03c |
Reserved |
|
0x040 |
Invert Field ID • bit 0 - invert_field_id[0] (Read/Write) • Others - reserved |
|
0x044 |
Reserved |
|
0x050 |
Write Frame Buffer • bit 31~0 - write_fb[31:0] (Read/Write) |
|
0x054 |
Write Frame Buffer • bit 31~0 - write_fb[63:32] (Read/Write)
|
|
0x058 |
Reserved |
|
Notes: 1. SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake. |
|