The synthesizable example design requires both Vivado® and Xilinx ® Vitis ™ software platform.
The first step is to run synthesis, implementation and bitstream generation in Vivado. After all those steps are done, select File > Export > Export Hardware . In the window, select Include bitstream , select an export directory and click OK .
Perform the following to generate the elf file (executable and linkable file) from the Vitis software platform.
1. Open the Vitis software platform.
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2. Go to File > New Application Project .
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3. Select a platform to create the project.
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4. Select the required xsa.
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5. Click Next .
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6. Name the application.
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7. Select the processor and click Next .
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8. Select the empty application.
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9. Import the required files.
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10. Build the project.
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11.
For the elf file, check the debug folder.
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Next, perform the following to run the application:
1. Connect a USB cable from the host PC to the USB JTAG port. Ensure the appropriate device drivers are installed.
2. Connect a second USB cable from the host PC to the USB UART port. Ensure that USB UART drivers are installed.
3. Connect the evaluation board to the power supply slot.
4. Switch on the board.
5. Start a terminal program (e.g., Hyper Terminal) on the host PC with the following settings for the standard COM port:
a. Baud Rate: 115200
b. Data Bits: 8
c. Parity: None
d. Stop Bits: 1
e. Flow Control: None
6. Right-click the xv_procss_example application in the project explorer window and click Build Project .
7. Right-click the xv_procss_example application and click Run As > Run Configurations .
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8. In the Run Configurations window, right-click Xilinx C/C++ application (System Debugger) and click New .
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X-Ref Target - Figure 5-15 |