The following table provides the register map of horizontal scaler registers in the video processing subsystem.
|
Register |
Description |
|---|---|
|
0x000 |
Control signals • bit 0 - ap_start (Read/Write/COH) • bit 1 - ap_done (Read/COR) • bit 2 - ap_idle (Read) • bit 3 - ap_ready (Read) • bit 7 - auto_restart (Read/Write) • Others - reserved |
|
0x004 |
Global Interrupt Enable Register • bit 0 - Global Interrupt Enable (Read/Write) • Others - reserved |
|
0x008 |
IP Interrupt Enable Register (Read/Write) • bit 0 - Channel 0 (ap_done) • bit 1 - Channel 1 (ap_ready) • Others - reserved |
|
0x00c |
IP Interrupt Status Register (Read/TOW) • bit 0 - Channel 0 (ap_done) • bit 1 - Channel 1 (ap_ready) • Others - reserved |
|
0x010 |
Height • bit 15~0 - HwReg_HeightIn[15:0] (Read/Write) • Others - reserved |
|
0x014 |
Reserved |
|
0x018 |
Input Width • bit 15~0 - HwReg_Width[15:0] (Read/Write) • Others - reserved |
|
0x01c |
Reserved |
|
0x020 |
Output Width • bit 15~0 - HwReg_HeightOut[15:0] (Read/Write) • Others - reserved |
|
0x024 |
Reserved |
|
0x028 |
Color Mode • bit 7~0 - HwReg_ColorMode[7:0] (Read/Write) • Others - reserved |
|
0x02c |
Reserved |
|
0x030 |
Pixel Rate • bit 31~0 - HwReg_PixelRate[7:0] (Read/Write) |
|
0x034 |
Reserved |
|
0x038 |
Ouput Color Mode • bit 7~0 - HwReg_ColorModeOut[7:0] (Read/Write) • Others - reserved |
|
0x0400 |
~ |
|
0x07ff |
Horizontal Filter Coefficients Address (384 * 16b) Word n: • bit [15: 0] - HwReg_hfltCoeff[2n] • bit [31:16] - HwReg_hfltCoeff[2n+1] |
|
0x4000 |
Phases Address (8192 * 9b) Word n: • bit [8: 0] - HwReg_phasesH_V[2n] • bit [24:16] - HwReg_phasesH_V[2n+1] • Others - reserved |