|
Subsystem Specifics |
| Supported Device Family
1
|
AMD UltraScale+™
Families,
AMD UltraScale™
Architecture, AMD Zynq™ 7000, AMD
7 series, AMD Versal™
Adaptive SoC |
| Supported User Interfaces |
AXI4-Lite, AXI4-Stream, AXI4
|
| Resources |
See Table 1
|
| Provided with
Subsystem
|
| Design Files |
Encrypted HLS C |
| Example Design |
Verilog |
| Test Bench |
Not Provided |
| Constraints File |
XDC |
| Simulation Model |
Not Provided |
| Supported S/W Driver
2
|
Standalone, Linux |
| Tested Design
Flows
3
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado Design Suite
|
| Support |
| Release Notes and Known Issues |
Master Answer Record: 65449
|
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Support web
page
|
- For a complete list of supported devices, see the AMD Vivado™
IP catalog.
- Standalone driver details can be found in
Vitis directory
(<install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm).
Linux: Linux OS and driver support information is available from the Xilinx Wiki page.
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|