The following table provides the register map of letterbox registers in video processing subsystem.
|
Register |
Description |
|---|---|
|
0x000 |
Control signals • bit 0 - ap_start (Read/Write/COH) • bit 1 - ap_done (Read/COR) • bit 2 - ap_idle (Read) • bit 3 - ap_ready (Read) • bit 7 - auto_restart (Read/Write) • Others - reserved |
|
0x004 |
Global Interrupt Enable Register • bit 0 - Global Interrupt Enable (Read/Write) • Others - reserved |
|
0x008 |
IP Interrupt Enable Register (Read/Write) • bit 0 - Channel 0 (ap_done) • bit 1 - Channel 1 (ap_ready) • Others - reserved |
|
0x00c |
IP Interrupt Status Register (Read/TOW) • bit 0 - Channel 0 (ap_done) • bit 1 - Channel 1 (ap_ready) • Others - reserved |
|
0x010 |
Width • bit 15~0 - HwReg_width[15:0] (Read/Write) • Others - reserved |
|
0x014 |
Reserved |
|
0x018 |
Height • bit 15~0 - HwReg_height[15:0] (Read/Write) • Others - reserved |
|
0x01c |
Reserved |
|
0x020 |
Video Format • bit 15~0 - HwReg_video_format[15:0] (Read/Write) • Others - reserved |
|
0x024 |
Reserved |
|
0x028 |
Column Start • bit 15~0 - HwReg_col_start[15:0] (Read/Write) |
|
0x02c |
Reserved |
|
0x030 |
Column End • bit 15~0 - HwReg_col_end[15:0] (Read/Write) • Others - reserved |
|
0x034 |
Reserved |
|
0x038 |
Row Start • bit 15~0 - HwReg_row_start[15:0] (Read/Write) • Others - reserved |
|
0x03c |
Reserved |
|
0x040 |
Row End • bit 15~0 - HwReg_row_end[15:0] (Read/Write) • Others - reserved |
|
0x044 |
Reserved |
|
0x048 |
Y or R • bit 15~0 - HwReg_Y_R_value[15:0] (Read/Write) • Others - reserved |
|
0x04c |
Reserved |
|
0x050 |
Cb or G • bit 15~0 - HwReg_Cb_G_value[15:0] (Read/Write) • Others - reserved |
|
0x054 |
Reserved |
|
0x058 |
Cr or B • bit 15~0 - HwReg_Cr_B_value[15:0] (Read/Write) • Others - reserved |
|
0x05c |
Reserved |
|
Notes: 1. SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake. |
|
Refer to the following register description applicable to above tables-
Notes:
1. The Control Register controls the operation of the core. Bit[0] of the Control register, ap_start , kicks off the core from software. Writing 1 to this bit, starts the core to generate a video frame. Bit[1] of the Control register, ap_done , indicates when the IP has completed all operations in the current transaction. A logic 1 on this signal indicates that the IP has completed all operations in this transaction. Bit[2] of the Control register, ap_idle , signal indicates if the IP is operating or idle (no operation). The idle state is indicated by logic 1. This signal is asserted low once the IP starts operating. This signal is asserted high when the IP completes operation and no further operations are performed. Bit[3] of the Control register, ap_ready , signal indicates when the IP is ready for new inputs. It is set to logic 1 when the IP is ready to accept new inputs, indicating that all input reads for this transaction are completed. If the IP has no operations in the pipeline, new reads are not performed until the next transaction starts. This signal is used to make a decision on when to apply new values to the input ports and whether to start a new transaction. Bit[7] of the Control register, auto_restart , can be set to enable the auto-restart mode. Thereafter, the IP restarts automatically at the end of each transaction.
2. Control Register (0x0000), Global Interrupt Enable Register (0x0004), IP Interrupt Enable Register (0x0008), and IP Interrupt Status Register (0x000C) are explained in section S_AXILITE Control Register Map of Vitis High-Level Synthesis User Guide ( UG1399) [Ref 12] . These registers definitions may have some additional bits; however, in the current IP, we are accessing only bits mentioned in Table: Vertical Scaler Registers . Therefore, only these bits need to be considered while accessing the Control Register, Global Interrupt Enable Register, IP Interrupt Enable Register, and IP Interrupt Status Register.