The following table provides the register map of Vertical scaler registers in the video processing subsystem.
Table 2-11:
Vertical Scaler Registers
|
Register
|
Description
|
|
0x000
|
Control signals
•
bit 0 - ap_start (Read/Write/COH)
•
bit 1 - ap_done (Read/COR)
•
bit 2 - ap_idle (Read)
•
bit 3 - ap_ready (Read)
•
bit 7 - auto_restart (Read/Write)
•
Others - reserved
|
|
0x004
|
Global Interrupt Enable Register
•
bit 0 - Global Interrupt Enable (Read/Write)
•
Others - reserved
|
|
0x008
|
IP Interrupt Enable Register (Read/Write)
•
bit 0 - Channel 0 (ap_done)
•
bit 1 - Channel 1 (ap_ready)
•
others - reserved
|
|
0x00c
|
IP Interrupt Status Register (Read/TOW)
•
bit 0 - Channel 0 (ap_done)
•
bit 1 - Channel 1 (ap_ready)
•
Others - reserved
|
|
0x010
|
Input Height
•
bit 15~0 - HwReg_HeightIn[15:0] (Read/Write)
•
Others - reserved
|
|
0x014
|
Reserved
|
|
0x018
|
Width
•
bit 15~0 - HwReg_Width[15:0] (Read/Write)
•
Others - reserved
|
|
0x01c
|
Reserved
|
|
0x020
|
Output Height
•
bit 15~0 - HwReg_HeightOut[15:0] (Read/Write)
•
Others - reserved
|
|
0x024
|
Reserved
|
|
0x028
|
Line Rate
•
bit 31~0 - HwReg_LineRate[31:0] (Read/Write)
|
|
0x02c
|
Reserved
|
|
0x030
|
Color Mode
•
bit 7~0 - HwReg_ColorMode[7:0] (Read/Write)
•
Others - reserved
|
|
0x034
|
Reserved
|
|
0x800
|
Vertical Filter Coefficients Address (64 * NR TAPS * 16b)
Word n :
•
bit [15: 0] - HwReg_vfltCoeff[2n]
•
bit [31:16] - HwReg_vfltCoeff[2n+1]
|