The Protocol Configuration Register [1:0] can be used to dynamically configure the active lanes used by the subsystem using the following guidelines:
1. Program the required lanes in the Protocol Configuration register (only allowed when Enable Active Lanes is set in the Vivado IDE).
2. The subsystem internally updates the new lanes information after the current packet complete indication is seen (for example, when the current active lanes indicate a Stop state condition) and a subsequent RxByteClkHS signal is seen on the PPI.
3. A read from the Protocol Configuration register reflects the new value after the subsystem has successfully updated the new lanes information internally.
4. Do not send the new updated lanes traffic until the read from Protocol Configuration registers reflects the new value.
The Active Lane bit field will not be updated if the
is absent. This will be indicated by the MIPI DPHY RX Clock lane being in stop state. After updating the active lanes field, if the MIPI DPHY RX Clock lane is in the stop state, you can continue without waiting for the Active Lane bit field getting updated. When the DPHY RX Clock Lane is out of the stop state, you can check for this field to get updated with programmed value.