The Clock Lane Information register is described in the following table. The Stop state is captured in this register.
| Bits | Name | Reset Value | Access | Description |
|---|---|---|---|---|
| 31–2 | Reserved | N/A | N/A | Reserved |
| 1 | Stop state | 0x0 | R | Stop state on clock lane |
| 0 | Reserved | N/A | N/A | Reserved |