Core Status Register - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)

Document ID
PG232
Release Date
2023-11-06
Version
5.4 English

The Core Status register is described in the following table.

Table 1. Core Status Register (0x10)
Bits Name Reset Value Access Description
31–16 Packet Count 0x0 R

Counts number of long packets written to the line buffer

  • Packet count rolls over from 0xFFFF to 0x0000. The roll over of this counter is not reported.
  • Count includes error packets (if any)
15–4 Reserved N/A N/A N/A
3 Short packet FIFO Full 0x0 R Indicates the current status of short packet FIFO full condition
2 Short packet FIFO not empty 0x0 R FIFO not empty: Indicates the current status of short packet FIFO not empty condition
1 Stream Line buffer Full 0x0 R Indicates the current status of line buffer full condition
0

Soft reset/Core disable

in progress

0x0 R Set to 1 by the core to indicate that internal soft reset/core disable activities are in progress