Dynamic VC Selection Register - 5.3 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

Document ID
PG232
Release Date
2023-05-16
Version
5.3 English

The VC Selection register described below allows you to dynamically select the VC packets to be processed by the core. The user needs to set “Allowed VC” GUI setting to “All” to use this feature. Packets that are filtered as part of this VC selection will not be counted in Core status register field- “Packet Count.” “Frame received” bit in Interrupt Status Register will not be set if VC disabling occurs before the “Frame End” packet is received.

Table 2-26: VC Selection Register (0x2C)

Bits

Name

Reset Value

Access

Description

31:16

Reserved

N/A

N/A

Reserved

15:0

VC Selection

0xFFFF

R/W

1: Core processes packets with this VC.

0: Core filters packets with this VC.

For example: VC Selection = 0x000E, means all packets with VC=3,2,1 are processed. Other packets are filtered out.

Bits 15:4 are used only when "Support VCX Feature" is enabled.

Writing 1 or 0 to 15:4 when "Support VCX Feature" is not enabled, will not have any impact.