Example 1 - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)

Document ID

PG232

Release Date

2023-11-06

Version

5.4 English

When RAW12 and RAW8 are transferred with two pixels per clock, the data port width of the video_out interface is 24 bits. Within the 24bits, the RAW8 pixels are aligned to the most significant bits as shown in the following table.

Important: In a multi-pixel scenario, pixel width varies, and pixels with lower width are justified to the most significant bit.

Table 1. Pixel Packing for RAW12 and RAW8 Data Types
Bit Positions	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RAW12	q11	q10	q9	q8	q7	q6	q5	q4	q3	q2	q1	q0	p11	p10	p9	p8	p7	p6	p5	p4	p3	p2	p1	p0
RAW8	q7	q6	q5	q4	q3	q2	q1	q0					p7	p6	p5	p4	p3	p2	p1	p0
p0 to p11 is the first pixel bits of RAW12; q0 to q11 is the second pixel bits of RAW12. p0 to p7 is the first pixel bits of RAW8; q0 to q7 is the second pixel bits of RAW8.