- Support for 1 to 4 D-PHY lanes
- Line rates ranging from 80 to 3200 Mbps
- Multiple Data Type support (RAW, RGB, YUV)
- Filtering based on Virtual Channel Identifier
- Support for 1, 2, or 4 pixels per clock at the output as defined in the AMD AXI4-Stream Video IP and System Design Guide (UG934) [Ref 2] format
- AXI4-Lite interface for register access to configure different subsystem options
- Dynamic selection of active lanes within the configured lanes during subsystem generation.
- Interrupt generation to indicate subsystem status information
- Internal D-PHY allows direct connection to image sources
- Support for MIPI CSI-2 standard v2.0 features such as VCX, RAW16, and RAW20