MIPI standard serial I/O ports should use MIPI_DPHY_DCI for the I/O standard in the XDC file for the UltraScale+ family. The LOC and I/O standards must be specified in the XDC file for all input and output ports of the design. The MIPI CSI-2 RX Subsystem and MIPI D-PHY sub-core generate the I/O pin LOC for the pins that are selected during IP customization. No I/O pin LOCs are provided for AMD 7 series FPGA designs. You need to manually select the clock capable I/O for AMD 7 series FPGA RX clock lane and restrict the I/O selection within the I/O bank.
It is recommended to select the I/O bank with the VRP pin connected for UltraScale+ MIPI CSI-2 RX Subsystem configurations. If the VRP pin is present in other I/O banks in the same I/O column of the device, the following DCI_CASCADE XDC constraint should be used. For example, I/O bank 65 has a VPR pin, and the D-PHY TX IP is using the IO bank 66.
set_property DCI_CASCADE {66}
[get_iobanks 65]