The MIPI CSI-2 RX Controller programming sequence is as follows and This Figure shows a graphical representation of the sequence:
1. After power on reset ( video_aresetn ), the core enable bit is, by default, set to 1 so the core starts processing packets sent on the PPI. The Active Lanes parameter is set to Maximum Lanes (configured in the Vivado IDE using the Serial Data Lanes parameter).
2. Disabling and re-enabling the core
° Disable the core using the Core Configuration Register (set the Core Enable bit to 0 or the Soft reset bit to 1).
° Wait until the core clears the Soft reset/Core enable in progress bit by reading the Core Status Register .
° Change the required core settings (for example, enabling interrupts)
° Re-enable the core (set the Core Enable bit to 1 or the Soft Reset bit to 0)
IMPORTANT: The MIPI CSI-2 RX Subsystem is initialized only when the required duration of LP-11 is observed as per the specification.