Protocol Configuration Register - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)
Document ID
PG232
Release Date
2023-11-06
Version
5.4 English

The Protocol Configuration register is described in the following table and allows you to configure protocol specific options such as the number of lanes to be used.

Table 1. Protocol Configuration Register (0x04)
Bits Name Reset Value Access Description
31–5 Reserved N/A N/A Reserved
4–3 Maximum Lanes Number of lanes configured during core generation R

Maximum lanes of the core

0x0—1 Lane

0x1—2 Lanes

0x2—3 Lanes

0x3—4 Lanes
2 Reserved N/A   Reserved
1–0 Active Lanes Number of lanes configured during core generation R/W

Active lanes in the core

0x0—1 Lane

0x1—2 Lanes

0x2 —3 Lanes

0x3—4 Lanes
  1. Maximum Lanes cannot exceed the number of lanes as set by the Serial Data Lanes parameter at generation time.
  2. A read from this register reflects the current number of lanes being used by core. This is useful when dynamically updating the active lanes during core operation to ensure that the core is using the new active lanes information. See Designing with the Subsystem for more information.
  3. Active Lanes cannot exceed the Maximum Lanes as set in the Protocol Configuration register setting of bits 4–3.