Shared Logic - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)
Document ID
PG232
Release Date
2023-11-06
Version
5.4 English

Shared Logic provides a flexible architecture that works both as a stand-alone subsystem and as part of a larger design with one of more subsystem instances. This minimizes the amount of HDL modifications required, but at the same time retains the flexibility of the subsystem.

Shared logic in the CSI-2 RX Subsystem allows you to share PLLs with multiple instances of the CSI-2 RX Subsystem within the same I/O bank.

There is a level of hierarchy called <component_name>_support. The following figures show two hierarchies where the shared logic is either contained in the subsystem or in the example design. In these figures, <component_name> is the name of the generated subsystem. The difference between the two hierarchies is the boundary of the subsystem. It is controlled using the Shared Logic option in the Vivado IDE Shared Logic tab for the MIPI CSI-2 RX Subsystem. The shared logic comprises a PLL and some BUFGs (maximum of four).

Figure 1. Shared Logic Included in the Subsystem Page-1 Sheet.16 Sheet.3 <Component Name>_exdes <Component Name>_exdes Process.2 <Component Name> <Component Name> Process.3 <Component Name>_support <Component Name>_support Ellipse Shared Logic Shared Logic Process.5 <Component Name>_core <Component Name>_core Sheet.8 X16320-030816 shadow8-18 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 X16320-030816
Figure 2. Shared Logic Outside the Subsystem Page-1 Sheet.45 Process.2 IPI System IPI System Process.3 <Component Name> <Component Name> Ellipse Shared Logic Shared Logic Process.5 <Component Name>_core <Component Name>_core Sheet.37 X16321-033116 shadow6-14 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 X16321-033116