Shared Logic provides a flexible architecture that works both as a stand-alone subsystem and as part of a larger design with one of more subsystem instances. This minimizes the amount of HDL modifications required, but at the same time retains the flexibility of the subsystem.
Shared logic in the CSI-2 RX Subsystem allows you to share PLLs with multiple instances of the CSI-2 RX Subsystem within the same I/O bank.
There is a level of hierarchy called <component_name>_support. This Figure and This Figure show two hierarchies where the shared logic is either contained in the subsystem or in the example design. In these figures, <component_name> is the name of the generated subsystem. The difference between the two hierarchies is the boundary of the subsystem. It is controlled using the Shared Logic option in the Vivado IDE Shared Logic tab for the MIPI CSI-2 RX Subsystem. The shared logic comprises a PLL and some BUFGs (maximum of 4).