The Shared Logic tab page provides shared logic inclusion parameters. The subsystem shared logic configuration screen is shown in This Figure .
Shared Logic: Select whether the PLL are included in the core or in the example design. Values are:
• Include Shared Logic in core
• Include Shared Logic in example design
• MMCM Sharing Across the banks when you select Include Shared Logic in the core
• Select to use MMCM externally for line rates >1500
X-Ref Target - Figure 4-4
X-Ref Target - Figure 4-5