VC Mapping - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)

Document ID
PG232
Release Date
2023-11-06
Version
5.4 English

In the event of an ErrEccDouble error, the VC is mapped to the VC reported in the current packet header (even if corrupted).

In the event of an ErrSotSyncHS error, the VC is mapped to the previous VC processed because, in this case, the packet header is not available.

Table 1. Frame Level Error
Set Condition(s) Set by the core after an FE when the data payload received between FS and FE contains errors.
Reset Sequence Write 1 to clear this bit.
Priority Set condition takes priority over reset sequence.
Impact Current packet being processed does not have any impact but the payload might be corrupted.