The Application Example Design demonstrates the use of the MIPI CSI-2 RX Subsystem and MIPI DSI TX Subsystem on an AMD Zynq™ UltraScale+ ™ ZCU102 board. On the capture path, the system receives images captured by an IMX274 image sensor. Processed images are displayed on either the HDMI monitor or the MIPI DSI display.
A block diagram of the MIPI CSI-2 Rx Subsystem application example design is shown in This Figure .
The MIPI CSI-2 RX Subsystem decodes, processes video data and presents on AXI4-Stream data with two pixels data per clock. The RAW video data is then converted into RGB data using the Demosaic IP, V_Gamma_Lut, V_Proc_SS CSC IPs, two pixels at a time.
RGB data is then fed to the Video Test Pattern Generator IP (V-TPG). The TPG is available in the design to act as an alternate source of video in case no MIPI CSI-2 video source is present. The TPG (in pass-through mode) sends video packets across the AXI4-Stream data in dual pixel per beat mode to an AXI4-Stream broadcaster.
The broadcaster is used to broadcast the stream to the MIPI DSI TX Subsystem or HDMI TX Subsystem to be displayed. The HDMI TX Subsystem is available as an alternative if a MIPI DSI-compliant display panel is not available. Using the GPIO IP, one of the destination video paths is selected. The GPIO enables the TREADY signal in the selected path. If the MIPI DSI TX Subsystem path is chosen, the video is passed through a video processing subsystem configured as a Scaler. This is required as the MIPI DSI Panel works on a fixed resolution of 1920x1200. All videos must either be up scaled (480p, 720p, 1080p) or downscaled (4K) to 1920x1200 resolution for the MIPI DSI display panel.
The entire system runs at 150 MHz video clock frequency.
Note: You must have the hardware evaluation license for the following IPs to build the complete design:
° MIPI CSI-2 RX Subsystem
° MIPI DSI TX Subsystem
° HDMI TX Subsystem
° Test pattern generator