The read path of the lane management block in the CSI-2 RX Controller operates on a 32-bit data path (irrespective of the number of lanes) and uses the video clock for processing the data. Therefore, the minimum required video clock for line rates ≤ 1500 Mbps should be greater than or equal to the effective PPI clock divided by four.
The following examples illustrate this:
- For a MIPI interface with 1000 Mbps per lane, 1 lane design, the effective rate at which the lane management block is written is 125 MHz. Because the lane management block read path operates on a 32-bit (4-byte) data path, the minimum required video clock is 125 MHz/4 or higher.
- For a MIPI interface with 800 Mbps, 2 lane design, the effective rate at which the lane management block is written is 100 MHz * 2. Because the lane management block read path operates on a 32–bit (4-byte) data path, the minimum required video clock is (100 MHz * 2)/4 or higher.
- For a MIPI interface with 700 Mbps per lane, 3 lane design, the effective rate at which the lane management block is written is 87.5 MHz * 3. Because the lane management block read path operates on a 32-bit (4-byte) data path, the minimum required video clock is (87.5 MHz * 3)/4 or higher.
- For a MIPI interface with 1200 Mbps per lane, 4 lane design, the effective rate at which the lane management block is written is 150 MHz * 4. Because the lane management block read path operates on 32-bit (4-byte) data path, the minimum required video clock is (150 MHz * 4)/4 or higher.
Apart from the minimum video clock requirement mentioned above, it is equally important to ensure that at any given time, the output bandwidth of the subsystem is greater than or equal to the input bandwidth.
The following examples illustrate this:
- For a MIPI interface with 1000 Mbps per lane, 1 lane, 2 pixel per clock design, processing RAW10 data, the minimum required video clock is (1000 *1) /(2*10) or higher, where 10 is the number of bits in one RAW10 pixel.
- For a MIPI interface with 600 Mbps per lane, 4 lanes, single pixel mode design, processing YUV420 8-bit data, the minimum required video clock is (600*4)/(1*8) or higher, where 8 is the number of bits in one 8-bit YUV420 pixel.
- Similarly, for a MIPI interface with 1200 Mbps per lane, 4 lane, dual pixel mode design, processing YUV420 8-bit data, the minimum required video clock is (1200*4)/(2*8) or higher, where 8 is the number of bits in one pixel.
The following equation is used to calculate the minimum required video clock:
video_aclk1 (MHz) = Line Rate (Mbps) * Data Lanes / (8*4) video_aclk2 (MHz) = (Line Rate (Mbps) * Data Lanes ) /(Pixels per Clock * Number of Bits Per Pixel)
The effective minimum required video clock is:
video_aclk (MHz) = Max
{video_aclk1, video_aclk2}
For line rates greater than 1500 Mbps, there is no limitation to the read path of the lane management block in the MIPI CSI-2 RX Controller. So, the effective minimum required clock for line rates >1500 Mbps is:
video_aclk (MHz) =
video_aclk2
When the Video Format Bridge is not included and line-rate <= 1500 Mbps, the video_aclk calculation does not depend on the Pixel Format and Pixels Per Clock selection.
video_aclk (Mhz) =
video_aclk1
When the Video Format Bridge is not
included and line-rate > 1500 Mbps, the
video_aclk calculation does not depend on
Pixel Format and Pixels Per Clock selection.
video_aclk (Mhz) =
rxbyteclkhs