Example Design Tab - 3.2 English

HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235)

Document ID
PG235
Release Date
2023-10-18
Version
3.2 English

The Example Design tab is shown in the following figure.

Figure 1. Example Design Tab
Design Topology
Allows you to choose the topology of example design to be generated. The allowable options are Pass-Through, TX Only, and Pass-Through+ I2S Audio (ZCU102 Only).
  • Pass-Through showcases the HDMI system built with one HDMI TX Subsystem and one HDMI RX Subsystem, sharing the same Video PHY Controller/HDMI GT Subsystem.
  • Tx-Only showcases the HDMI system built with only one HDMI TX Subsystem and Video PHY Controller . A Frame CRC helper core is added to the Tx-Only topology to facilitate system monitor and debugging. An illustration is shown in the following figure.
    Figure 2. TX-Only Topology with Frame CRC Help Core
    Figure 3. TX-Only Topology with Frame CRC Help Core
  • Pass-Through + I2S Audio (ZCU102 Only) showcases the I2S Audio functionality using HDMI as carrier for the video. Unlike the Pass-Through design, the HDMI RX Audio is forwarded to HDMI TX to playback. In Pass-Through + I2S Audio system, the HDMI RX audio is forwarded to I2S TX. Similarly, the I2S RX audio is passed to HDMI TX for playback. A system illustration is shown in the following figure.
Axilite Frequency
Allows you to choose the AXI4-Lite CPU clock. In this release, the following options have been verified.
7 series
50 MHz, 100 MHz, 150 MHz
UltraScale/UltraScale+ Devices
50 MHz, 100 MHz, 150 MHz, 200 MHz
Versal Adaptive SoCs
100 MHz
Video Phy Controller Setting
Allows the configuration of the Transmitter PLL type and Receiver PLL Type to the Video PHY Controller /HDMI GT Subsystem prior generating the example design. It also allows user to selectively opt-out the NI-DRU to optimize resource use if the video resolution they plan to support does not require NI-DRU. See the Video PHY Controller LogiCORE IP Product Guide (PG230) or the HDMI GT Controller LogiCORE IP Product Guide (PG334) for details about NI-DRU requirements for Versal adaptive SoCs.
Example Design Overview
A system block diagram to show the overview of the example design to be generated.
Important: When the example design targets the VCU118 board and Design Topology is set to Pass-Through, the Include NIDRU option under the Video PHY Controller setting is grayed out and unchecked by default.
Note: When the AXI4-Lite clock is set at a higher frequency, it is more likely to have timing violations. You must adjust the clock rate to achieve timing closure without impacting system performance.